TS555 block diagram The TS555 is a single CMOS timer with a very low consumption. This device comes in three different package NDIP, SOIC and TSSOP. Since it low power consumption, the TS555 timing remains accurate in both monostable and astable mode. The TS555 provides reduced supply current spikes during output transitions, which enable the use of lower decoupling capacitors compared to those required by bipolar NE555.

In monostable mode, the timer operates like a one-shot generator. The external capacitor is initially held discharged by a transistor inside the timer.

The following datasheet outlines detail information about STM TS555 low power single CMOS timer. Here you will find description of the device, features, absolute maximum ratings and operating conditions, block diagram, schematic diagram, electrical characteristics, application information, package information, ordering information and revision history of the datasheet.

Free download PDF file of STM TS555 low power single CMOS timer here.

Source: st.com



Related Post

LM161|LM361 High Speed Differential Comparators Datasheet and Schematics
HLB122I Power Transistor Datasheet and Schematics
ADV7180 Multiformat Video Decoder - PAL NTSC SECAM - Circuit Diagram Application and Datasheet
4 Wire Series/Parallel Stepper Motor Wiring Configuration
IEEE 1284-A Parallel Port Connector Pinout Schematic Diagram